1. Field of the Invention
The present invention relates to a storage circuit control device and the method thereof, and a graphic computation device and the method thereof, capable of simultaneously processing image data for multiple pixels, and moreover efficiently using the storage area of the storage circuit.
2. Description of the Related Art
Computer graphics are often used in various CAD (Computer Aided Design) systems, amusement devices, and so forth. Particularly, recent advancements in image processing technology has given rise to rapid propagation of systems using three-dimensional computer graphics.
With such three-dimensional computer graphics, rendering processing is performed in order to display the graphics on a display such as a CRT (Cathode Ray Tube) having pixels arrayed in matrix fashion.
In this rendering processing, the color data for each pixel is calculated, and the obtained color data is written to a display buffer (frame buffer) corresponding with the pixel. One of the techniques for rendering processing is polygon rendering. With this technique, a three-dimensional model is expressed as a combination of triangular unit shapes (polygons), and drawing is performed in units of these polygons, thereby determining the color of the display screen.
With three-dimensional computer graphics systems using such polygon rendering, texture mapping processing is performed at the time of drawing. This texture mapping processing reads texture data indicating an image pattern from a texture buffer in units of triangles, and pasts this read texture data onto the surface of the three-dimensional model, so as to obtain highly realistic image data.
With the texture mapping processing, as shown below, a two-dimensional texture address for specifying a pixel projecting an image according to the image data is calculated, and this is used as a texture address to make reference to texture data stored in the texture buffer.
Specifically, first, the (s, t, q) of each pixel within the triangle is calculated from linear interpolation, based on the (s1, t1, q1), (s2, t2, q2), and (s3, t3, q3) indicating the homogeneous coordinates (s, t) of the apexes of the triangle and the homogeneous item q.
Now, in simple terms, the homogeneous item q is the ratio of enlargement or reduction.
Next, division yields the (s/q, t/q) for each pixel, the s/q and t/q are each multiplied by the texture size USIZE and VSIZE, thereby generating texture coordinates data (u, v).
Next, the texture coordinates data (u, v) is converted into a texture address (U, V) on the texture buffer, and this texture address (U, V) is used to read the texture data from the texture buffer.
With three-dimensional computer graphics systems such as described above, the texture data may be stored in a two-dimensional array corresponding to a U and V coordinates system in the storage area of the texture buffer, so that direct reference can be made to the texture buffer using the texture address (U, V). That is to say, the two-dimensional texture address (U, V) may be directly used to access texture data stored in the texture buffer. This method simplifies the processing for accessing the texture data.
However, there is a problem with this method, in that storing multiple types of texture data in the texture buffer results in available area which cannot be efficiently used as shown in FIG. 12, due to the relation between the size of the texture data to be stored and the size of the available area, and consequently the storage area cannot be efficiently used.
For example, as shown in FIG. 12, in the event of storing pieces of texture data 400, 401, 402, 403, and 406, each with differing address lengths in the U and V directions, within the address space of the texture buffer so that direct reference can be made with the texture address (U, V), available areas 410 and 411 where texture data cannot be stored is created due to the relation between the two-dimensional size of the texture data to be stored and the two-dimensional size of the available area.
Consequently, a texture buffer having an extremely great storage capacity in comparison to the amount of texture data to be stored must be used, increasing the scale of the system and raising costs.
Accordingly, conventional systems calculate a one-dimensional physical address A from a two-dimensional address (U, V), based on xe2x80x9cphysical address A=Vxc3x97(texture width)+Uxe2x80x9d, and use this physical address A to access the texture buffer, in order to use the storage area of the texture buffer in an efficient manner. Thus, texture data can be stored without creating an available area in the storage area of the texture buffer, as shown in FIG. 13.
Incidentally, xe2x80x9ctexture widthxe2x80x9d refers to the address length in the U direction, in the address space of the texture buffer.
FIG. 14 is a partial configuration diagram of a conventional three-dimensional computer graphic system.
As shown in FIG. 14, the physical address A for each pixel is calculated from the (s1, t1, q1), (s2, t2, q2), and (s3, t3, q3) of the apex of the triangle as described above, in the address converting device 104 built into the texture mapping device 101. Then, using this calculated physical address A, the texture data (R, G, B, xcex1) is read from the texture buffer 102 to the texture mapping device 101, this texture data (R, G, B, xcex1) is pasted to the pixels corresponding to the surface of the three-dimensional model, thereby generating plotting data S101. This plotting data S101 is written to the display buffer 103.
Also, with high-speed three-dimensional computer graphics systems, as shown in FIG. 15 for example, an n number of texture mapping devices 1011 through 101n each having built-in address converting devices 1041 through 104n, and texture mapping processing is simultaneously performed for an n number of pixels in a parallel manner, thereby simultaneously writing the plotting data S1011 through S101n to the display buffer.
Now, three-dimensional computer graphics systems such as described above may perform processing by simultaneously reading image data of pixels arrayed within a certain rectangle in a 2-by-2 or 4-by-4 matrix form.
However, using the physical address A generated by xe2x80x9cphysical address A=Vxc3x97(texture width)+Uxe2x80x9d may make it difficult to guarantee that simultaneously read image data will be stored in different banks in the texture buffer.
Accordingly, with conventional three-dimensional computer graphics systems, access to the texture buffer regarding image data for simultaneous processing of multiple pixels has been made using two-dimensional texture addresses (U. V). Accordingly, as described above, there is the problem that the storage area of the texture buffer cannot be used efficiently.
The present invention has been made in light of the problems with the conventional art, and accordingly, it is an object of the present invention to provide a storage circuit control device and a graphic computation device capable of efficiently using the storage area of the texture buffer with a small circuit configuration, and moreover enabling simultaneous processing of image data for multiple pixels.
It is another object of the present invention to provide a storage circuit control method and a graphic computation method capable of efficiently using the storage area of the texture buffer, and moreover enabling simultaneous processing of image data for multiple pixels.
In order to solve the above-described problems with the conventional art, and to achieve the above objects, the storage circuit control device according to the present invention is a storage circuit control device which stores in a storage circuit two-dimensional image data including pixel data indicating the color of a plurality of pixels arrayed in matrix fashion, and simultaneously accesses the pixel data regarding the plurality of pixels stored in the storage circuit using a two-dimensional address (U, V) corresponding to the two-dimensional positioning of the plurality of pixels;
wherein storage to the storage circuit is performed such that unit blocks, including the plurality of pixel data to be simultaneously accessed, are stipulated, and stored in the storage circuit so that a plurality of unit blocks making up the two-dimensional image data are continuously positioned within a one-dimensional address space within the storage circuit.
The storage circuit preferably may have at least a number of banks corresponding to the pixel data to be simultaneously accessed, wherein each piece of the simultaneously-accessed plurality of pixel data included in the unit blocks is stored in mutually differing banks in the storage circuit.
Also, the simultaneously-accessed plurality of pixel data may consist of pixel data for a plurality of pixels arrayed in matrix fashion.
Further, the storage circuit control device may comprise: an address generating means for combining the bit data making up the U address of the two-dimensional address (U, V) represented by n bits (wherein n is an integer of 1 or greater) and the bit data making up the V address of the two-dimensional address (U, V) represented by m bits (wherein m is an integer of 1 or greater), so as to generate an (n+m) bit one-dimensional address; and data accessing means for accessing the storage circuit using the generated one-dimensional address.
Also, in the event that
the integer n and the integer m are equal;
k is an integer expressed by (nxe2x88x921) less than k less than 0;
the U address is represented by the n bits of (U [nxe2x88x921], . . . , U[k], . . . , U[0]);
and the V address is represented by the n bits of (V[nxe2x88x921], V[k], . . . , V[0]);
the address generating means may combine each of the bit data U[nxe2x88x921], . . . , U[k], . . . , U[0] of the U address with each of the bit data V[nxe2x88x921], . . . , V[k], . . . , V[0] of the V address, thereby generating 2n bits of one-dimensional addresses (V[nxe2x88x921], U[nxe2x88x921], . . . , V[k], U[k], . . . , V[0], U[0]).
According to a graphic computation device according to a first aspect of the present invention, a three-dimensional model is represented by a combination of a plurality of unit shapes, and addresses corresponding to the homogeneous coordinates (s, t) and the homogeneous item q included in the pixel data representing the color of each pixel positioned within the unit shapes are used to simultaneously read a plurality of pixel data stored in the storage circuit making up texture data which is image data to be pasted to the unit shapes and perform the pasting thereof to the unit shapes, the graphic computation device comprising:
a storage circuit to which storage is performed such that unit blocks, comprising the plurality of pixel data to be simultaneously accessed, are stipulated, and stored so that a plurality of unit blocks making up the texture data are continuously positioned within a one-dimensional address space within the storage circuit;
a two-dimensional address generating means for generating two-dimensional addresses (U, V) based on the results of dividing the homogeneous coordinates (s, t) by the homogeneous item q, i.e., (s/q, s/t);
a one-dimensional address generating means for generating one-dimensional addresses from the two-dimensional addresses (U, V); and
a data reading means for using the generated one-dimensional addresses to read the texture data from the storage circuit in units of the unit blocks, and perform pasting thereof to the unit shapes.
With the graphic computation device according to the first aspect of the present invention, two-dimensional addresses (U, V) are generated at the two-dimensional address generating means, based on the results of dividing the homogeneous coordinates (s, t) by the homogeneous item q, i.e., (s/q, s/t).
Next, one-dimensional addresses are generated from the above-generated two-dimensional addresses, at the one-dimensional address generating means.
Next, at the data reading means, the above generated one-dimensional addresses are used to read the texture data from the storage circuit in units of the unit blocks, and paste the unit blocks to the unit shapes.
According to the graphic computation device according a second aspect of to the present invention, a three-dimensional model is represented by a combination of a plurality of unit shapes, and addresses corresponding to the homogeneous coordinates (s, t) and the homogeneous item q included in the pixel data representing the color of each pixel positioned within the unit shapes are used to simultaneously read a plurality of pixel data stored in the storage circuit making up texture data which is image data to be pasted to the unit shapes and perform the pasting thereof to the unit shapes, the graphic computation device comprising:
a storage circuit to which storage is performed such that unit blocks, comprising the plurality of pixel data to be simultaneously accessed, are stipulated, and stored so that a plurality of unit blocks making up the texture data are continuously positioned within a one-dimensional address space within the storage circuit;
a polygon rendering data generating means for generating polygon rendering data regarding the apex of the unit shape, including data for three-dimensional coordinates (x, y, z), R (red), G (green), B (blue), and homogeneous coordinates (s, t) and homogeneous item q;
an interpolation data generating means for interpolating the polygon rendering data for the apex of the unit shape, and generating interpolation data for pixels positioned within the unit shape;
a two-dimensional address generating means for generating two-dimensional addresses (U, V) based on the results of dividing the homogeneous coordinates (s, t) included in the interpolation data by the homogeneous item q, i.e., (s/q, s/t);
a one-dimensional address generating means for generating one-dimensional addresses from the two-dimensional addresses (U, V); and
a data reading means for using the generated one-dimensional addresses to read the texture data from the storage circuit in units of the unit blocks, and perform pasting thereof to the unit shapes.
With the graphic computation device according to the second aspect of the present invention, first, polygon rendering data regarding the apex of the unit shape, including data for three-dimensional coordinates (x, y, z), R (red), G (green), B (blue), and homogeneous coordinates (s, t) and homogeneous item q, is generated at the polygon rendering data generating means.
Next, at the interpolation data generating means, the polygon rendering data for the apex of the unit shape is interpolated, and interpolation data for pixels positioned within the unit shape is generated.
Next, the two-dimensional addresses (U, V) are generated at the two-dimensional address generating means, based on the results of dividing the homogeneous coordinates (s, t) included in the interpolation data by the homogeneous item q, i.e., (s/q, s/t).
Then, the one-dimensional addresses are generated at the one-dimensional address generating means from the above-generated two-dimensional addresses (U, V).
Further, at the data reading means, the generated one-dimensional addresses are used to read the texture data from the storage circuit in units of the unit blocks, and paste the unit blocks to the unit shapes.
According to the graphic computation device according to a third aspect of the present invention, a three-dimensional model is represented by a combination of a plurality of unit shapes, wherein addresses corresponding to the homogeneous coordinates (s, t) and the homogeneous item q included in the pixel data representing the color of each pixel positioned within the unit shapes are used to simultaneously read a plurality of pixel data stored in the storage circuit making up texture data which is image data to be pasted to the unit shapes and perform the pasting thereof to the unit shapes, the graphic computation device comprising:
a polygon rendering data generating device for generating polygon rendering data regarding the apex of the unit shape, including data for three-dimensional coordinates (x, y, z), R (red), G (green), B (blue), and homogeneous coordinates (s, t) and homogeneous item q;
a rendering device for performing rendering processing using the polygon rendering data; and
a bus for connecting the polygon rendering data generating device and the rendering device;
wherein the rendering device comprises:
a storage circuit to which storage is performed such that unit blocks, comprising the plurality of pixel data to be simultaneously accessed, are stipulated, and stored so that a plurality of unit blocks making up the texture data are continuously positioned within a one-dimensional address space within the storage circuit;
an interpolation data generating means for interpolating the polygon rendering data input from the polygon rendering data generating device via the bus, and generating interpolation data for pixels positioned within the unit shape;
a two-dimensional address generating means for generating two-dimensional addresses (U, V) based on the results of dividing the homogeneous coordinates (s, t) included in the interpolation data by the homogeneous item q, i.e., (s/q, s/t);
a one-dimensional address generating means for generating one-dimensional addresses from the two-dimensional addresses (U, V); and
a data reading means for using the generated one-dimensional addresses to read the texture data from the storage circuit in units of the unit blocks, and perform pasting thereof to the unit shapes.
With the graphic computation device according to the third aspect of the present invention, polygon rendering data regarding the apex of the unit shape, including data for three-dimensional coordinates (x, y, z), R (red), G (green), B (blue), and homogeneous coordinates (s, t) and homogeneous item q, is generated at the polygon rendering data generating device. This polygon rendering data is transferred to the rendering device via the bus.
Next, the following processing is performed in the rendering device.
That is, the polygon rendering data input from the polygon rendering data generating device via the bus is interpolated at the interpolation data generating means, and interpolation data for pixels positioned within the unit shape is generated.
Next, two-dimensional addresses (U, V) are generated at the two-dimensional address generating means, based on the results of dividing the homogeneous coordinates (s, t) included in the interpolation data by the homogeneous item q, i.e., (s/q, s/t).
Next, one-dimensional addresses are generated at the one-dimensional address generating means from the above-generate two-dimensional addresses (U, V).
Then, the data reading means uses the generated one-dimensional addresses to read the texture data from the storage circuit in units of the unit blocks, and paste the unit blocks to the unit shapes.
Also, the storage circuit control method according to the present invention is a storage circuit control method for storing in a storage circuit two-dimensional image data including pixel data indicating the color of a plurality of pixels arrayed in matrix fashion, and simultaneously accessing the pixel data regarding the plurality of pixels stored in the storage circuit using a two-dimensional address (U, V) corresponding to the two-dimensional positioning of the plurality of pixels;
wherein storage to the storage circuit is performed such that unit blocks, including the plurality of pixel data to be simultaneously accessed, are stipulated, and stored in the storage circuit so that a plurality of unit blocks making up the two-dimensional image data are continuously positioned within a one-dimensional address space within the storage circuit.
Further, according to the graphic computation method according to the present invention, a three-dimensional model is represented by a combination of a plurality of unit shapes, and addresses corresponding to the homogeneous coordinates (s, t) and the homogeneous item q included in the pixel data representing the color of each pixel positioned within the unit shapes are used to simultaneously read a plurality of pixel data stored in the storage circuit making up texture data which is image data to be pasted to the unit shapes and perform the pasting thereof to the unit shapes, the graphic computation method comprising the steps of:
storing in a storage circuit such that unit blocks, comprising the plurality of pixel data to be simultaneously accessed, are stipulated, and stored so that a plurality of unit blocks making up the texture data are continuously positioned within a one-dimensional address space within the storage circuit;
generating two-dimensional addresses (U, V) based on the results of dividing the homogeneous coordinates (s, t) by the homogeneous item q, i.e., (s/q, s/t);
generating one-dimensional addresses from the two-dimensional addresses (U, V); and
using the generated one-dimensional addresses to read the texture data from the storage circuit in units of the unit blocks and perform pasting thereof to the unit shapes.